The present disclosure relates to a successive approximation AD converter, and more particularly to a technology for improving AD conversion precision.
AD converters have various architectures, which are used differently depending on the required specifications. A successive approximation AD converter is configured to obtain a multi-bit digital signal by repeating comparison operation between an analog input voltage and a voltage generated by a digital-to-analog converter (hereinafter referred to as a DAC) successively from the highest-order bit. Therefore, the converter can be formed only of a comparator, a DAC, and a simple digital circuit, serving as an architecture most likely to achieve reduction in size and power consumption.
The conversion precision of the successive approximation AD converter largely depends on the precision of the DAC. As the DAC, a capacitance array having capacitance values weighted with a binary ratio is generally used. In particular, for a high-resolution capacitance DAC, a technique of dividing the capacitance array into a higher-order DAC and a lower-order DAC and coupling such DACs to each other by a coupling capacitor is used to suppress increase in the capacitance values of the capacitance array.
Reducing the size of capacitor elements increases mismatches and variations of the capacitance values, causing an error in weighting between higher-order part and lower-order part. An error also occurs in the weighting with a binary ratio for higher-order bits for which a precise capacitance ratio is particularly required. As a result, the output characteristics of the capacitance DAC become nonlinear, worsening the conversion precision of the successive approximation AD converter. Such nonlinear characteristics of the converted output result in generating a noise tone on the output spectrum, causing degradation in spurious free dynamic range (SFDR). For this reason, it has been considered difficult to use the successive approximation AD converter in the fields requiring high SFDR such as the communication and audio fields.
As a technique of preventing or reducing the tone on the output spectrum, a dithering technique has been proposed where noise having no periodicity is applied to the input signal (see U.S. Pat. No. 7,286,075 (Patent Document 1), for example).
Also proposed has been a technique of preventing or reducing a nonlinear error caused by a weighting error between higher-order part and lower-order part of a capacitance DAC by adjusting a variable capacitor placed in the lower-order part (see U.S. Pat. No. 7,928,880 (Patent Document 2), for example).